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tisp4070m3aj thru tisp4115m3aj, tisp4125m3aj thru tisp4220m3aj, tisp4240m3aj thru tisp4395m3aj bidirectional thyristor overvoltage protectors product information 1 august 2001 - revised december 2001 copyright ? 2001, power innovations limited, uk information is current as of publication date. products conform to specifications in accordance with the terms of power innovations standard warranty. production processing does not necessarily include testing of all parameters. telecommunication system 50 a 10/1000 overvoltage protectors a bourns company 4 kv 10/700, 100 a 5/310 itu-t k.20/21 rating sma (do-214ac) package 25 % smaller placement area than smb low differential capacitance . . . . . . . 39 pf ion-implanted breakdown region precise and stable voltage low voltage overshoot under surge device v drm v v (bo) v ?4070 58 70 ?4080 65 80 ?4090 68 90 ?4095 75 95 ?4115 90 115 ?4125 100 125 ?4145 120 145 ?4165 135 165 ?4180 145 180 ?4200 155 200 ?4220 160 220 ?4240 180 240 ?4250 190 250 ?4265 200 265 ?4290 220 290 ?4320 240 320 ?4300 230 300 ?4350 275 350 ?4360 290 360 ?4395 320 395 rated for international surge wave shapes . wave shape standard i tsp a 2/10 s gr-1089-core 300 8/20 s iec 61000-4-5 220 10/160 s fcc part 68 120 10/700 s itu-t k.20/21/45 100 10/560 s fcc part 68 75 10/1000 s gr-1089-core 50 description these devices are designed to limit overvoltages on the telephone line. overvoltages are normally caused by a.c. power system or lightning flash disturbances which are induced or conducted on to the telephone line. a single device provides 2-point protection and is typically used for the protection of 2-wire telecommunication equipment (e.g. between the ring and tip wires for telephones and modems). combinations of devices can be used for multi-point protection (e.g. 3-point protection between ring, tip and ground). the protector consists of a symmetrical voltage-triggered bidirectional thyristor. overvoltages are initially clipped by breakdown clamping until the voltage rises to the breakover level, which causes the device to crowbar into a low-voltage on state. this low-voltage on state causes the current resulting from the overvoltage to be safely diverted through the device. the high crowbar holding current prevents d.c. latchup as the diverted current subsides. how to order device package carrier order as tisp4xxxm3aj aj (j-bend do-214ac/sma) embossed tape reeled tisp4xxxm3ajr insert xxx value corresponding to protection voltages of 070, 080, 090, 095 etcetera. device symbol t r sd4xaa t erminals t and r correspond to the alternative line designators of a and b mdxxcc smaj package (top view) 12 r (b) t (a)
tisp4070m3aj thru tisp4115m3aj, tisp4125m3aj thru tisp4220m3aj, tisp4240m3aj thru tisp4395m3aj bidirectional thyristor overvoltage protectors 2 august 2001 - revised december 2001 product information the tisp4xxxm3aj range consists of twenty voltage variants to meet various maximum system voltage levels (58 v to 320 v). they are guaranteed to voltage limit and withstand the listed international lightning surges in both polarities. these medium (m) current protection devices are in a plastic package smaj (jedec do-214ac with j-bend leads) and supplied in embossed tape reel pack. for alternative voltage and holding current values, consult the factory. for higher rated impulse currents, the 100 a 10/1000 tisp4xxxh3bj series in the smb (jedec do-214aa) package is available. absolute maximum ratings, t a = 25 c (unless otherwise noted) rating symbol value unit repetitive peak off-state voltage, (see note 1) ?4070 ?4080 ?4090 ?4095 ?4115 ?4125 ?4145 ?4165 ?4180 ?4200 ?4220 ?4240 ?4250 ?4265 ?4290 ?4300 ?4320 ?4350 ?4360 ?4395 v drm 58 65 68 75 90 100 120 135 145 155 160 180 190 200 220 230 240 275 290 320 v non-repetitive peak on-state pulse current (see notes 2, 3 and 4) i tsp a 2/10 s (gr-1089-core, 2/10 s voltage wave shape) 300 8/20 s (iec 61000-4-5, combination wave generator, 1.2/50 voltage, 8/20 current) 220 10/160 s (fcc part 68, 10/160 s voltage wave shape) 120 5/200 s (vde 0433, 10/700 s voltage wave shape) 110 0.2/310 s (i3124, 0.5/700 s voltage wave shape) 100 5/310 s (itu-t k.20/21/45, k.44 10/700 s voltage wave shape) 100 5/310 s (ftz r12, 10/700 s voltage wave shape) 100 10/560 s (fcc part 68, 10/560 s voltage wave shape) 75 10/1000 s (gr-1089-core, 10/1000 s voltage wave shape) 50 non-repetitive peak on-state current (see notes 2, 3 and 5) i tsm 23 24 1.6 a 20 ms (50 hz) full sine wave 16.7 ms (60 hz) full sine wave 1000 s 50 hz/60 hz a.c. initial rate of rise of on-state current, exponential current ramp, maximum ramp value < 100 a di t /dt 300 a/s junction temperature t j -40 to +150 c storage temperature range t stg -65 to +150 c notes: 1. see applications information and figure 10 for voltage values at lower temperatures. 2. initially the tisp4xxxm3aj must be in thermal equilibrium with t j =25c. 3. the surge may be repeated after the tisp4xxxm3aj returns to its initial conditions. 4. see applications information and figure 11 for current ratings at other temperatures. 5. eia/jesd51-2 environment and eia/jesd51-3 pcb with standard footprint dimensions connected with 5 a rated printed wiring track widths. see figure 9 for the current ratings at other durations. derate current values at -0.61 %/c for ambient temperatu res above 25 c
3 august 2001 - revised december 2001 tisp4070m3aj thru tisp4115m3aj, tisp4125m3aj thru tisp4220m3aj, tisp4240m3aj thru tisp4395m3aj bidirectional thyristor overvoltage protectors product information electrical characteristics, t a = 25 c (unless otherwise noted) parameter test conditions min typ max unit i drm repetitive peak off- state current v d = v drm t a = 25 c t a = 85 c 5 10 a v (bo) breakover voltage dv/dt = 250 v/ms, r source = 300 ? ?4070 ?4080 ?4090 ?4095 ?4115 ?4125 ?4145 ?4165 ?4180 ?4200 ?4220 ?4240 ?4250 ?4265 ?4290 ?4300 ?4320 ?4350 ?4360 ?4395 70 80 90 95 115 125 145 165 180 200 220 240 250 265 290 300 320 350 360 395 v v (bo) impulse breakover voltage dv/dt 1000 v/s, linear voltage ramp, maximum ramp value = 500 v di/dt = 20 a/s, linear current ramp, maximum ramp value = 10 a ?4070 ?4080 ?4090 ?4095 ?4115 ?4125 ?4145 ?4165 ?4180 ?4200 ?4220 ?4240 ?4250 ?4265 ?4290 ?4300 ?4320 ?4350 ?4360 ?4395 78 88 98 102 122 132 151 171 186 207 227 247 257 272 298 308 328 359 370 405 v i (bo) breakover current dv/dt = 250 v/ms, r source = 300 ? 0.15 0.6 a v t on-state voltage i t =5a, t w = 100 s 3 v i h holding current i t = 5 a, di/dt = +/-30 ma/ms 0.15 0.35 a dv/dt critical rate of rise of off-state voltage linear voltage ramp, maximum ramp value < 0.85v drm 5 kv/s i d off-state current v d =50v t a = 85 c 10 a
tisp4070m3aj thru tisp4115m3aj, tisp4125m3aj thru tisp4220m3aj, tisp4240m3aj thru tisp4395m3aj bidirectional thyristor overvoltage protectors 4 august 2001 - revised december 2001 product information c off off-state capacitance f=1mhz, v d =1v rms, v d =0, f=1mhz, v d =1v rms, v d =-1v f=1mhz, v d =1v rms, v d =-2v f=1mhz, v d =1v rms, v d =-50v f=1mhz, v d =1v rms, v d = -100 v (see note 6) 4070 thru ?4115 ?4125 thru ?4220 ?4240 thru ?4395 ?4070 thru ?4115 ?4125 thru ?4220 ?4240 thru ?4395 ?4070 thru ?4115 ?4125 thru ?4220 ?4240 thru ?4395 ?4070 thru ?4115 ?4125 thru ?4220 ?4240 thru ?4395 ?4125 thru ?4220 ?4240 thru ?4395 83 62 50 78 56 45 72 52 42 36 26 19 21 15 100 74 60 94 67 54 87 62 50 44 31 22 25 18 pf note 6: to avoid possible voltage clipping, the ?4125 is tested with v d =-98v. thermal characteristics parameter test conditions min typ max unit r ja junction to free air thermal resistance eia/jesd51-3 pcb, i t = i tsm(1000) , t a = 25 c, (see note 7) 115 c/w 265 mm x 210 mm populated line card, 4-layer pcb, i t = i tsm(1000) , t a = 25 c 52 note 7: eia/jesd51-2 environment and pcb has standard footprint dimensions connected with 5 a rated printed wiring track widths. electrical characteristics, t a = 25 c (unless otherwise noted) (continued) parameter test conditions min typ max unit
5 august 2001 - revised december 2001 tisp4070m3aj thru tisp4115m3aj, tisp4125m3aj thru tisp4220m3aj, tisp4240m3aj thru tisp4395m3aj bidirectional thyristor overvoltage protectors product information parameter measurement information figure 1. voltage-current characteristic for t and r terminals all measurements are referenced to the r terminal -v v drm i drm v d i h i t v t i tsm i tsp v (bo) i (bo) i d quadrant i switching characteristic +v +i v (bo) i (bo) v d i d i h i t v t i tsm i tsp -i quadrant iii switching characteristic pmxxaab v drm i drm
tisp4070m3aj thru tisp4115m3aj, tisp4125m3aj thru tisp4220m3aj, tisp4240m3aj thru tisp4395m3aj bidirectional thyristor overvoltage protectors 6 august 2001 - revised december 2001 product information typical characteristics figure 2. figure 3. figure 4. figure 5. off-state current vs junction temperature t j - junction temperature - c -25 0 25 50 75 100 125 150 |i d | - off-state current - a 0001 001 01 1 10 100 tcmag v d = 50 v normalised breakover voltage vs junction temperature t j - junction temperature - c -25 0 25 50 75 100 125 150 normalised breakover voltage 0.95 1.00 1.05 1.10 tc4maf on-state current vs on-state voltage v t - on-state voltage - v 0.7 1.5 2 3 4 5 7 110 i t - on-state current - a 1.5 2 3 4 5 7 15 20 30 40 50 70 1 10 100 t a = 25 c t w = 100 s tc4macc '4125 thru '4200 '4240 thru '4395 '4070 thru '4115 normalised holding current vs junction temperature t j - junction temperature - c -25 0 25 50 75 100 125 150 normalised holding current 0.4 0.5 0.6 0.7 0.8 0.9 1.5 2.0 1.0 tc4mad
7 august 2001 - revised december 2001 tisp4070m3aj thru tisp4115m3aj, tisp4125m3aj thru tisp4220m3aj, tisp4240m3aj thru tisp4395m3aj bidirectional thyristor overvoltage protectors product information typical characteristics figure 6. figure 7. figure 8. normalised capacitance vs off-state voltage v d - off-state voltage - v 0.5 1 2 3 5 10 20 30 50 100150 capacitance normalised to v d = 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 t j = 25c v d = 1 vrms tc4mabc '4070 thru '4115 '4125 thru '4200 '4240 thru '4395 differential off-state capacitance vs rated repetitive peak off-state voltage v drm - repetitive peak off-state voltage - v 50 60 70 80 90 150 200 250 300 350 100 ? ? ? ? c - differential off-state capacitance - pf 20 25 30 35 40 ? ? ? ? c = c off(-2 v) - c off(-50 v) tcmaeb typical capacitance asymmetry vs off-state voltage v d ? off-state voltage ? v 0.5 0.7 2 3 4 5 7 20 30 4050 110 | c off(+vd) - c off(-vd) | ? capacitance asymmetry ? pf 0 1 2 3 v d = 1 v rms, 1 mhz v d = 10 mv rms, 1 mhz tc4xbb
tisp4070m3aj thru tisp4115m3aj, tisp4125m3aj thru tisp4220m3aj, tisp4240m3aj thru tisp4395m3aj bidirectional thyristor overvoltage protectors 8 august 2001 - revised december 2001 product information rating and thermal information figure 9. figure 10. figure 11. non-repetitive peak on-state current vs current duration t - current duration - s 01 1 10 100 1000 i tsm(t) - non-repetitive peak on-state current - a 1.5 2 3 4 5 6 7 8 9 15 20 10 ti4mal v gen = 600 vrms, 50/60 hz r gen = 1.4*v gen /i tsm(t) eia/jesd51-2 environment eia/jesd51-3 pcb t a = 25 c v drm derating factor vs minimum ambient temperature t amin - minimum ambient temperature - c -35 -25 -15 -5 5 15 25 -40 -30 -20 -10 0 10 20 derating factor 0.93 0.94 0.95 0.96 0.97 0.98 0.99 1.00 ti4madb '4125 thru '4200 '4240 thru '4395 '4070 thru '4115 impulse rating vs ambient temperature t a - ambient temperature - c -40-30-20-10 0 1020304050607080 impulse current - a 40 50 60 70 80 90 100 120 150 200 250 300 400 iec 1.2/50, 8/20 itu-t 10/700 fcc 10/560 fcc 10/160 tc4maaa telcordia 10/1000 telcordia 2/10
9 august 2001 - revised december 2001 tisp4070m3aj thru tisp4115m3aj, tisp4125m3aj thru tisp4220m3aj, tisp4240m3aj thru tisp4395m3aj bidirectional thyristor overvoltage protectors product information applications information deployment these devices are two terminal overvoltage protectors. they may be used either singly to limit the voltage between two conductors (figure 12) or in multiples to limit the voltage at several points in a circuit (figure 13). in figure 12, protector th1 limits the maximum voltage between the two conductors to v (bo) . this configuration is normally used to protect circuits without a ground reference, such as modems. in figure 13, protectors th2 and th3 limit the maximum voltage between each conductor and ground to the v (bo) of the individual protector. protector th1 limits the maximum voltage between the two conductors to its v (bo) value. if the equipment being protected has all its vulnerable components connected between the conductors and ground, then protector th1 is not required. impulse testing to verify the withstand capability and safety of the equipment, standards require that the equipment is tested with various impulse wave forms. the table below shows some common values. if the impulse generator current exceeds the protectors current rating then a series resistance can be used to reduce the current to the protectors rated value and so prevent possible failure. the required value of series resistance for a given waveform is given by the following calculations. first, the minimum total circuit impedance is found by dividing the impulse generators peak voltage by the protectors rated current. the impulse generators fictive impedance (generators peak voltage divided by peak short circuit current) is then subtracted from the minimum total circuit impedance to give the required value of series resistance. for the fcc part 68 10/560 waveform the following values result. the minimum total circuit impedance is 800/75 = 10.7 ? and the generators fictive impedance is 800/100 = 8 ? . this gives a minimum series resistance value of 10.7 - 8 = 2.7 ? . after allowing for tolerance, a 3 ? 10% resistor would be suitable. the 10/160 waveform needs a standard resistor value of 5.6 ? per conductor. these would be r1a and r1b in figure 12. two point protection figure 13. multi-point protection standard peak voltage setting v voltage wave form s peak current value a current wave form s tisp4xxxm3 25 c rating a series resistance ? gr-1089-core 2500 2/10 500 2/10 300 11 1000 10/1000 100 10/1000 50 fcc part 68 (march 1998) 1500 10/160 200 10/160 120 2x5.6 800 10/560 100 10/560 75 3 1500 9/720 ? 37.5 5/320 ? 100 0 1000 9/720 ? 25 5/320 ? 100 0 i3124 1500 0.5/700 37.5 0.2/310 100 0 itu-t k.20/k.21 1500 4000 10/700 37.5 100 5/310 100 0 ? fcc part 68 terminology for the waveforms produced by the itu-t recommendation k.21 10/700 impulse generator th1 th3 th2 th1
tisp4070m3aj thru tisp4115m3aj, tisp4125m3aj thru tisp4220m3aj, tisp4240m3aj thru tisp4395m3aj bidirectional thyristor overvoltage protectors 10 august 2001 - revised december 2001 product information figure 15 and figure 16. fcc part 68 allows the equipment to be non-operational after the 10/160 (conductor to ground) and 10/560 (inter-conductor) impulses. the series resistor value may be reduced to zero to pass fcc part 68 in a non-operational mode e.g. figure 14. for this type of design, the series fuse must open before the tisp4xxxm3 fails. for figure 14, the maximum fuse i 2 t is 2.3 a 2 s. in some cases the equipment will require verification over a temperature range. by using the rated waveform values from figure 11, the appropriate series resistor value can be calculated for ambient temperatures in the range of -40 c to 85 c. a.c. power testing the protector can withstand currents applied for times not exceeding those shown in figure 9. currents that exceed these times must be terminated or reduced to avoid protector failure. fuses, ptc (positive temperature coefficient) resistors and fusible resistors are overcurrent protection devices which can be used to reduce the current flow. protective fuses may range from a few hundred milliamperes to one ampere. in some cases it may be necessary to add some extra series resistance to prevent the fuse opening during impulse testing. the current versus time characteristic of the overcurrent protector must be below the line shown in figure 9. in some cases there may be a further time limit imposed by the test standard (e.g. ul 1459 wiring simulator failure). capacitance the protector characteristic off-state capacitance values are given for d.c. bias voltage, v d , values of 0, -1 v, -2 v and -50 v. where possible values are also given for -100 v. values for other voltages may be calculated by multiplying the v d = 0 capacitance value by the factor given in figure 6. up to 10 mhz the capacitance is essentially independent of frequency. above 10 mhz the effective capacitance is strongly dependent on connection inductance. in many applications, such as figure 15 and figure 17, the typical conductor bias voltages will be about -2 v and -50 v. figure 7 shows the differential (line unbalance) capacitance caused by biasing one protector at -2 v and the other at -50 v. figure 8 shows the typical capacitance asymmetry; the difference between the capacitance measured with a positive value of v d and the capacitance value when the polarity of v d is reversed. capacitance asymmetry is an important parameter in adsl systems where the protector often has no d.c. bias and the signal level is in the region of 10 v. normal system voltage levels the protector should not clip or limit the voltages that occur in normal system operation. for unusual conditions, such as ringing without the line connected, some degree of clipping is permissible. under this condition about 10 v of clipping is normally possible without activating the ring trip circuit. figure 10 allows the calculation of the protector v drm value at temperatures below 25 c. the calculated value should not be less than the maximum normal system voltages. the tisp4265m3aj, with a v drm of 200 v, can be used for the protection of ring generators producing 100 v rms of ring on a battery voltage of -58 v (th2 and th3 in figure 17). the peak ring voltage will be 58 + 1.414*100 = 199.4 v. however, this is the open circuit voltage and the connection of the line and its equipment will reduce the peak voltage. in the extreme case of an unconnected line, clipping the peak voltage to 190 v should not activate the ring trip. this level of clipping would occur at the temperature when the v drm has reduced to 190/200 = 0.95 of its 25 c value. figure 10 shows that this condition will occur at an ambient temperature of -28 c. in this example, the tisp4265m3aj will allow normal equipment operation provided that the minimum expected ambient temperature does not fall below -28 c. jesd51 thermal measurement method to standardise thermal measurements, the eia (electronic industries alliance) has created the jesd51 standard. part 2 of the standard (jesd51-2, 1995) describes the test environment. this is a 0.0283 m 3 (1 ft 3 ) cube which contains the test pcb (printed circuit board) horizontally mounted at the centre. part 3 of the
11 august 2001 - revised december 2001 tisp4070m3aj thru tisp4115m3aj, tisp4125m3aj thru tisp4220m3aj, tisp4240m3aj thru tisp4395m3aj bidirectional thyristor overvoltage protectors product information standard (jesd51-3, 1996) defines two test pcbs for surface mount components; one for packages smaller than 27 mm on a side and the other for packages up to 48 mm. the smaj measurements used the smaller 76.2 mm x 114.3 mm (3.0 ? x 4.5 ?) pcb. the jesd51-3 pcbs are designed to have low effective thermal conductivity (high thermal resistance) and represent a worse case condition. the pcbs used in the majority of applications will achieve lower values of thermal resistance and so can dissipate higher power levels than indicated by the jesd51 values.
tisp4070m3aj thru tisp4115m3aj, tisp4125m3aj thru tisp4220m3aj, tisp4240m3aj thru tisp4395m3aj bidirectional thyristor overvoltage protectors 12 august 2001 - revised december 2001 product information typical circuits figure 14. modem inter-wire protection figure 15. protection module figure 16. isdn protection figure 17. line card ring/test protection fuse tisp4350 ai6xbma ring detector hook switch d.c. sink signal modem ring tip r1a r1b ring wire tip wire th3 th2 th1 protected equipment e.g. line card ai6xbk r1a r1b th3 th2 th1 ai6xbl signal d.c. test relay ring relay slic relay test equip- ment ring generator s1a s1b r1a r1b ring wire tip wire th3 th2 th1 th4 th5 slic slic protection ring/test protection over- current protection s2a s2b s3a s3b v bat c1 220 nf ai6xbj tisp6xxxx, tisppblx, ?tisp6ntp2
13 august 2001 - revised december 2001 tisp4070m3aj thru tisp4115m3aj, tisp4125m3aj thru tisp4220m3aj, tisp4240m3aj thru tisp4395m3aj bidirectional thyristor overvoltage protectors product information mechanical data recommended printed wiring land pattern dimensions. device symbolization code devices will be coded as below. as the device parameters are symmetrical, terminal 1 is not identified. carrier information for production quantities the carrier will be embossed tape reel pack. evaluation quantities may be shipped in bulk pack or embossed tape. device symbolization code tisp4070m3aj 4070m tisp4080m3aj 4080m tisp4090m3aj 4090m tisp4095m3aj 4095m tisp4115m3aj 4115m tisp4125m3aj 4125m tisp4145m3aj 4145m tisp4165m3aj 4165m tisp4180m3aj 4180m tisp4200m3aj 4200m tisp4220m3aj 4220m tisp4240m3aj 4240m tisp4250m3aj 4250m tisp4265m3aj 4265m tisp4290m3aj 4290m tisp4300m3aj 4300m tisp4320m3aj 4320m tisp4350m3aj 4350m tisp4360m3aj 4360m tisp4395m3aj 4395m carrier standard quantity embossed tape reel pack 5 000 sma land pattern mdxxbic all linear dimensions in millimeters and parenthetically in inches 2,34 [.092] 1,90 [.075] 2,16 [.085]
tisp4070m3aj thru tisp4115m3aj, tisp4125m3aj thru tisp4220m3aj, tisp4240m3aj thru tisp4395m3aj bidirectional thyristor overvoltage protectors 14 august 2001 - revised december 2001 product information mechanical data smaj (do-214ac) plastic surface mount diode package this surface mount package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. the compound will withstand soldering temperature with no deformation, and circuit performance characteristics will remain stable when operated in high humidity conditions. leads require no additional cleaning or processing when used in soldered assembly. sma mdxxcaa 4,57 [.180] 4,06 [.160] 5,59 [.220] 4,83 [.190] 2,92 [.115] 2,29 [.090] 2,40 [.095] 2,00 [.079] 2,16 [.085] 1,58 [.062] 1,52 [.060] 0,76 [.030] 0,20 [.008] 0,10 [.004] 1,63 [.064] 1,27 [.050] 2 index mark (if needed) all linear dimensions in millimeters and parenthetically in inches
15 august 2001 - revised december 2001 tisp4070m3aj thru tisp4115m3aj, tisp4125m3aj thru tisp4220m3aj, tisp4240m3aj thru tisp4395m3aj bidirectional thyristor overvoltage protectors product information mechanical data tape dimensions notes: a. the clearance between the component and the cavity must be within 0,05 mm (.002 in) min. to 0,65 mm (.026 in) max. so that the component cannot rotate more than 20 within the determined cavity. b. taped devices are supplied on a reel of the following dimensions:- reel diameter: 330 mm 3,0 mm (12.99 in .12 in) reel hub diameter 75 mm (2.95 in) min. reel axial hole: 13,0 mm 0,5 mm (.51 in .02 in) c. 5 000 devices per reel. mdxxcga index mark (if needed) 4,10 [.161] 3,90 [.154] 4,50 [.177] max. sma package single-sprocket tape all linear dimensions in millimeters and parenthetically in inches direction of feed 0 min. 12,30 [.484] 11,70 [.461] 1,65 [.065] 1,55 [.061] 4,10 [.161] 3,90 [.154] 2,05 [.081] 1,95 [.077] 1,5 [.059] min. carrier tape embossment 5,55 [.219] 5,45 [.215] 1,85 [.073] 1,65 [.065] cover tape 8,20 [.323] max. 20 typical component cavity centre line maximum component rotation typical component centre line 0,40 [.016] max.
tisp4070m3aj thru tisp4115m3aj, tisp4125m3aj thru tisp4220m3aj, tisp4240m3aj thru tisp4395m3aj bidirectional thyristor overvoltage protectors 16 august 2001 - revised december 2001 product information important notice power innovations limited (pi) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to verify, before placing orders, that the information being relied on is current. pi warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with pi's standard warranty. testing and other quality control techniques are utilized to the extent pi deems necessary to support t his warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. pi assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. nor is any license, either express or implied, granted under any patent right, copyright, design right, or other intellectual property right of pi covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. pi semiconductor products are not designed, intended, authorised, or warranted to be suitable for use in life-support applications, devices or systems. copyright ? 2001, power innovations limited

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